• 专利附录
  • 专利说明
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    • 专利摘要:
    Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a primary semiconductor layer constrained over a buried oxide layer. Elements of the epitaxial base layer are used to modify a state of stress in the primary semiconductor layer, within a first region of the multi-layer substrate, without modifying a state of stress of the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed for each of them to include a portion of the primary semiconductor layer, within the first region of the multi-layer substrate, and a second plurality of transistor channel structures. is formed so that each of them comprises a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures made by these methods may include transistor channel structures having different states of stress.
    公开号:FR3026224A1
    申请号:FR1558527
    申请日:2015-09-14
    公开日:2016-03-25
    发明作者:Bich-Yen Nguyen；Mariam Sadaka；Christophe Malville
    申请人:Soitec SA；
    IPC主号:
    专利说明:

    [0001] METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURES INCLUDING FIXED STRUCTURES HAVING DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR STRUCTURES TECHNICAL FIELD [00011 Embodiments of the present invention relate to methods that can be used to fabricate solid state transistors. N-type metal-oxide-semiconductor (NMOS) field effect and P-type metal-oxide-semiconductor (PMOS) field effect transistors having different stress states in a common layer on a semiconductor substrate as well as semiconductor structures and semiconductor devices manufactured by these methods. BACKGROUND OF THE INVENTION Semiconductor devices, such as microprocessors and memory devices, employ semiconductor transistors as the primary, basic operating structure of their integrated circuits. The field effect transistor (FET) is a type of transistor commonly used in semiconductor structures and semiconductor devices, which typically includes a source contact, a drain contact, and one or more gate contacts. A region of the semiconductor channel extends between the source contact and the drain contact. One or more PN junctions is (are) defined between the source contact and the gate contact. The gate contact is adjacent to at least a portion of the channel region, and the conductivity thereof is varied by the presence of an electric field. An electric field is therefore provided in the region of the channel, applying a voltage to the gate contact. Thus, for example, the electric current can pass through the transistor from the source contact to the drain contact, through the region of the channel, when a voltage is applied to the gate contact, but not from the source contact to the drain contact, in the absence of application. voltage at the gate contact. [0003] Recently developed field effect transistors (FETs) employ discrete, elongated channel structures called "fins." This type of transistors is often referred to in the art as "finned FETs." Many different configurations of finned FETs have been proposed in the art. [0004] The elongated channel or finned structures of a finned FET comprise a semiconductor material which can be N or P doped. It has also been demonstrated that the conductivity of N-doped semiconductor materials can be improved when the N-type semiconductor material is in a tensile stress state, as is the conductivity of P-type semiconductor materials, when the P-type semiconductor material is in a state of compressive stress . Currently used fin FETs have cross sections less than 22 nm. These transistors can employ depleted (undoped) channels that improve their electrostatic performance and avoid problems associated with random dopant fluctuations. It has been shown that the introduction of a tensile stress in the channel region of a transistor can improve the electron mobility of N-type FETs, and that the introduction of compressive stress into the channel region of a transistor can improve the mobility of P-type FET holes. SUMMARY OF THE INVENTION [0006] The present disclosure is intended to present a selection of concepts in simplified form, which will be detailed in the description below. examples of embodiments. This statement is not intended to identify the main or essential features of the claims, nor to be used to limit the scope thereof. In some embodiments, the present invention includes a method of manufacturing a semiconductor structure. A proposed multi-layer substrate includes a base substrate, an oxide layer buried on a surface of the base substrate, a primary semiconductor layer constrained to one side of the buried oxide layer, opposite the base substrate , and an epitaxial base layer on one side of the strained semiconductor layer, opposite the buried oxide layer. The elements are diffused from the epitaxial base layer into the strained primary semiconductor layer within a first region of the multi-layer substrate without diffusion of elements of the epitaxial base layer into the semiconductor layer. constrained primary conductor, within a second region of the multi-layer substrate, and a concentration of diffused elements is enriched in the primary semiconductor layer, within the first region, so that a state stress in the primary semiconductor layer, within the first region, differs from a state of stress in the primary semiconductor layer, within the second region. A first plurality of transistor channel structures are formed such that each includes a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of The transistor channel is formed so that each of them comprises a portion of the primary semiconductor layer within the second region of the multilayer substrate. In further embodiments, the present invention includes a method of manufacturing a semiconductor structure, wherein a multi-layer substrate, provided, includes a base substrate, an oxide layer buried on a a surface of the base substrate, a primary semiconductor layer constrained on one side of the buried oxide layer, opposite the base substrate, and an epitaxial base layer on one side of the stressed semiconductor layer, the opposite of the buried oxide layer. A first region of the multi-layer substrate is masked by a first mask layer, and a portion of the epitaxial base layer is removed from a second region of the multi-layer substrate. The first mask layer is removed from the first region of the multi-layer substrate, and the second region of the multi-layer substrate is masked by a second mask layer. The elements are scattered from the epitaxial base layer in the strained primary semiconductor layer, within the first region of the multilayer substrate, and a stress state of the primary semiconductor layer, indoors of the first region of the multi-layer substrate, is modified, without diffusion of elements in the constrained primary semiconductor layer, within the second region of the multi-layer substrate. A first plurality of transistor channel structures are formed for each of them to include a portion of the primary semiconductor layer, within the first region of the multi-layer substrate, and a second plurality of channel structures. transistor is formed so that each of them comprises a portion of the primary semiconductor layer within the second region of the multi-layer substrate. In other embodiments, the present invention includes a semiconductor structure including a multi-layer substrate that includes a base substrate, an oxide layer buried on a surface of the base substrate, and a layer primary semiconductor on one side of the buried oxide layer, opposite the base substrate. A portion of the primary semiconductor layer within a first region of the multi-layer substrate comprises SiyGei.y, wherein y is from about 0.20 to about 0.99, and a portion of the primary semiconductor layer, within a second region of the multi-layer substrate having constrained Si in tension. The portion of the primary semiconductor layer, within the first region of the multilayered substrate, has a crystallographic stress differing from a crystallographic stress of the portion of the primary semiconductor layer, indoors of the second region of the multi-layer substrate.
    [0002] BRIEF DESCRIPTION OF THE DRAWINGS [0010] Although the description ends with claims in particular signaling and distinctly claiming the embodiments of the invention, the advantages of embodiments of the description will be more readily apparent from that of certain exemplary embodiments. embodiment of the invention, taken in conjunction with the accompanying drawings, in which: [0011] FIGS. 1 to 4 show a schematic simplified sectional view illustrating the manufacture of a multi-layer substrate that can be used according to the modes embodiment of the present invention; FIG. 1 illustrates the implantation of ions in a donor substrate including a mass material, an epitaxial base layer, and a stressed primary semiconductor layer, the implanted ions forming a zone of weakness inside. the epitaxial base layer; Figure 2 illustrates the bonding of the donor substrate of Figure 1 to a receiving substrate; Figure 3 illustrates the separation of the donor substrate along the zone of weakness; FIG. 4 illustrates a multi-layer substrate formed during the separation of the donor substrate along the zone of weakness, as illustrated in FIG. 3; FIG. 5 illustrates a first mask layer covering a first region of the multi-layer substrate of FIG. 4, while another second region of the multi-layer substrate is not covered and exposed through the first layer. mask; Figure 6 illustrates the semiconductor structure of Figure 5 after removal of a portion of the epitaxial base layer from above the primary semiconductor layer in the second region of the multi-layer substrate, while another portion of the epitaxial base layer remains in place on the primary semiconductor layer, under the first mask layer of Figure 5 in the first region of the multi-layer substrate; Figure 7 illustrates a structure formed by removing the first mask layer from the first region of the multi-layer substrate, and providing a second mask layer on the primary semiconductor layer, in the second region of the substrate. multi-layer; Figures 8A-8C are enlarged views of a portion of the first region of the multi-layer substrate, illustrating a condensation process used to diffuse one or more elements, from the epitaxial base layer into the semiconductor layer. primary conductor, in the first region of the multi-layer substrate, for modifying a state of stress within the primary semiconductor layer, in the first region of the multi-layer substrate; Figure 9 illustrates a plurality of fin structures formed by etching through the primary semiconductor layer of the structure of Figure 7; and [0021] Figure 10 illustrates an exemplary structure of a fin FET transistor. DETAILED DESCRIPTION [0022] The illustrations presented here are not actual views of a particular structure, device, system or semiconductor process, but merely idealized representations. , used to describe embodiments of the invention. The headers used herein should not be considered as limiting the scope of the embodiments of the invention, as defined by the claims below and their legal equivalents. The concepts described in a specific header generally apply in other sections throughout the description.
    [0003] 100241 The terms first and second in the description and claims serve to distinguish between similar elements. As used herein, the terms "fins" and "fin structure" refer to a defined, finite, three-dimensional, elongated volume of semiconductor material having a length, a width, and a height, wherein the length is greater than the width. In some embodiments, the width and height of the fins may vary along their length. The methods that can be used to fabricate semiconductor devices are described below with reference to the figures. As discussed in more detail below, the methods generally include providing a multi-layered substrate that includes a base substrate, a buried oxide layer (BOX) on a surface of the base substrate, a primary semiconductor layer constrained on one side of the BOX layer, opposite the base substrate, and an epitaxial base layer on one side of the stressed semiconductor layer, opposite the BOX layer. The epitaxial base layer may comprise a layer on which the primary semiconductor layer has been previously formed by epitaxial growth, as set forth below. After providing the multilayer substrate, the multilayer substrate can be processed to modify a state of stress in a region of the primary semiconductor layer, without modifying a state of stress in another region of the primary semiconductor layer, so that there exist regions with different states of stress in the primary semiconductor layer. N-type transistor structures can then be fabricated in a region or regions of the primary semiconductor layer having a preferable stress state to increase electron mobility, and P-type transistor structures can be fabricated in a region or regions of the primary semiconductor layer having a preferable stress state to increase the mobility of the holes. Examples of embodiments that can be used to provide a multi-layer substrate are described below with reference to Figures 1-4. Figure 1 illustrates a donor substrate 100 which includes a mass material 102, an epitaxial basecoat 104 on the mass material 102, and a constrained semiconductor layer 106 on one side of the epitaxial basecoat 104, the ground material 102 may comprise a chip or wafer, for example, of semiconductor material (silicon, silicon carbide, germanium, III-V semiconductor material, etc.). ), ceramic material (silicon oxide, aluminum oxide, silicon carbide, etc.), or metal material (molybdenum, etc.). In some embodiments; the mass material 102 may have a monocrystalline or polycrystalline microstructure. In other embodiments, the mass material 102 may be amorphous. The mass material 102 may have a thickness of, for example, from about 400 μm to about 900 μm (e.g., about 750 μm). The layers covering the mass material 102, such as the epitaxial base layer 104 and the primary semiconductor layer 106, can be deposited or "drawn" on the substrate epitaxially, by means of one of several methods. such as, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PLD), vapor phase epitaxy (VPE), and molecular beam epitaxy (MBE). In some embodiments, the epitaxial basecoat 104 may comprise a material that can be used to help maintain a stress in the crystal lattice of the overlapping primary semiconductor layer 106 upon subsequent processing. as explained in more detail below. The epitaxial base layer 104 may therefore have a composition and / or a thickness selected to allow the epitaxial base layer 104 to maintain the stress in the crystal lattice of the overlapping primary semiconductor layer 106, during a subsequent treatment. as discussed in more detail lo hereinafter. The primary semiconductor layer 106 may comprise, for example, a layer of constrained silicon (Si), of constrained germanium (Ge), of silicon-germanium constraint (SiGe) or of a semiconductor material III-V constrained. Thus, the constrained primary semiconductor material 106 may have a crystal structure having lattice parameters that are either above (tensile stress) or below (compressive stress) the relaxed lattice parameters that would normally be presented. by the crystalline structure of the constrained semiconductor layer 106, if it existed in an isolated and non-epitaxial manner, at the equilibrium state. The primary semiconductor layer 106 may have an average thickness of about 50 nm or less, or even about 35 nui or less, although thicker layers of constrained semiconductor material may also be employed in embodiment of the present invention. One or more buffer layer (s) 108 may optionally be provided between the mass material 102 and the epitaxial base layer 104 to facilitate the epitaxial growth of the epitaxial base layer. 104 and the primary semiconductor layer 106 on the mass material 102. [0033] By way of specific nonlimiting example, the mass material 102 of the donor substrate 100 may comprise a monocrystalline silicon substrate, the base layer epitaxial 104, of SixGel_x (wherein x is from about 0.01 to 0.99 or, more specifically, from about 0.20 to about 0.80), and the primary semiconductor layer 106 from constrained silicon (sSi) or SiyGel..y constrained (where y is between about 0.20 and 0.99). In some embodiments, the SixGel 2 of the epitaxial basecoat 104 may comprise at least substantially relaxed Si.Ge 1+; In other words, the SixGei of the epitaxial base layer 104 may be at least substantially free of crystallographic stress in some embodiments. [0034] One or more buffer layers 108 comprising SizGel_z (in which the value of z increases progressively stepwise or continuously away from the mass material 102) can or can be provided (s) between the silicon of the material 102 and the epitaxial base layer of Si.Gel_x 104. [0035] The value of x in the epitaxial base layer of SiGei_. 104 may be selected to obtain a desired level of stress in the Si or SiyGel_y overlying the primary semiconductor layer 106. As is known in the art, there is a 4.2% network mismatch. between Si and Ge. Thus, the amount of Ge in the epitaxial base layer of SixGel.), 104 will at least partially determine the values of the lattice parameters in this layer, and hence the amount of crystallographic stress in the crystal lattice of SiGei_x of the overlapping epitaxial primary semiconductor layer 106. The epitaxial base layer 104 and the primary semiconductor layer 106 may have thicknesses less than their respective critical thicknesses, so as to avoid relaxation and initial defect formation. located in the corresponding crystal structure. After forming or otherwise providing the donor substrate 100 of FIG. 1, the primary semiconductor layer 106 and at least a portion of the epitaxial base layer 104 can be transferred to a receiving substrate 110 (FIG. using, for example, what is known in the art as a SMARTCUTO process. The SMARTCUTe process is described, for example, in US Patent No. RE 39,484 to Bruel (issued February 6, 2007), No. 6,303,468 to Aspar et al. (issued October 16, 2001), No. 6,335,258 to Aspar et al. (issued January 1, 2002), No. 6,756,286 to Monceau et al. (issued June 29, 2004), No. 6,809,044 to Aspar et al. (issued Oct. 26, 2004), and No. 6,946,365 to Aspar et al. (issued September 20, 2005), the descriptions of which are hereby incorporated in their entirety by reference. A plurality of ions (e.g., hydrogen ions, helium ions, or inert gas ions) may be implanted in the donor substrate 100. For example, ions may be implanted in the donor substrate 100 by a ion source placed on one side of the donor substrate 100, as represented by the directional arrows 109 in FIG. 1. The ions can be implanted in the donor substrate 100 in a direction substantially perpendicular to the major surfaces of the donor substrate 100. As is known in the art, the implantation depth of the ions in the donor substrate 100 is at least partially a function of the energy of this implantation. In general, ions implanted with less energy will be at relatively lower depths, while ions implanted with higher energy will be at relatively higher depths. The ions can be implanted in the donor substrate 100 with a predetermined energy, selected to implant the ions to a desirable depth in the donor substrate 100. By way of non-limiting example, the ions can be arranged in the substrate donor 100, at a selected depth, so as to form a zone of weakness in the donor substrate 100. As is known in the art, it is inevitable that at least some ions can be implanted at different depths of the depth desired implantation, and a graph of the concentration of ions, as a function of the depth in the donor substrate 100, from the surface thereof, may have a generally bell-shaped (symmetrical or asymmetrical) curve, having a maximum at a desirable implantation depth.
    [0004] When implanted in the donor substrate 100, the ions may define an area of weakness 112 (illustrated by a dashed line in FIG. 1) in the donor substrate 100. The zone of weakness 112 may comprise a layer or region within the donor substrate 100, which is aligned with (eg, centered on) the plane of maximum concentration of the ions with the donor substrate 100. The zone of weakness 112 may define a plane within the substrate donor 100, along which the latter can be cleaved or fractured in a subsequent process. As shown in FIG. 1, the zone of weakness 112 may be disposed within a substantially homogeneous region of the donor substrate, comprising the epitaxial basecoat 104. [00411] After formation of the zone of weakness 112 at the In the interior of the donor substrate 100, the latter may be bonded to the recipient substrate 110, as shown in FIG. 2, using a direct molecular bonding method. The direct molecular bonding process can form direct atomic bonds between the donor substrate 100 and the recipient substrate 110. The nature of the atomic bonds 9 between the donor substrate 100 and the receiving substrate 110 will depend on the compositions of the materials on the surfaces of the each of the donor substrate 100 and the recipient substrate 110. In some embodiments, the direct bond between the donor substrate bonding surface 100 and the receptor substrate binding surface 110 can be established by forming each of the bonding the donor substrate 100 and the bonding surface of the receiving substrate 110 to obtain relatively smooth surfaces, then contacting the bonding surfaces and initiating the propagation of a bonding wave therebetween. For example, each of the bonding surface of the donor substrate 100 and the bonding surface of the receiving substrate 110 may be formed to obtain an average roughness value (RMS) of about two nanometers (2.0 nm) or less, about one nanometer (1.0 nm) or less, or about one quarter of a nanometer (0.25 nm) or less. Each of the bonding surface of the donor substrate 100 and the bonding surface of the receiving substrate 110 may be softened using one or more of a mechanical polishing operation and a chemical etching operation. For example, it is possible to resort to a chemical mechanical planarization (CMP) to flatten and / or reduce the surface roughness of each of the surface of the donor substrate 100 and the bonding surface of the receiving substrate 110. 10044 After softening the bonding surfaces, these may optionally be cleaned and / or activated by methods known in the art. Such an activation method can be used to modify the surface chemistry to the right of the bonding surfaces, so as to facilitate the bonding process and / or to allow the formation of a stronger bond. The bonding surfaces can be brought into direct physical contact, and pressure can be applied in a localized area on the bonding interface. Interatomic bonds may be initiated in the vicinity of the localized pressure zone, and a link wave may propagate in the interface between the bonding surfaces. Optionally, one can use an annealing process to strengthen the bond. This method may include heating the bonded donor substrate 100 and the receiving substrate 110 in an oven at a temperature of from about 100 degrees Celsius (100 ° C) to about 400 degrees Celsius (400 ° C) for a period of time of about two minutes (2 minutes) and about fifteen hours (15 hours). An insulating layer 114 (such as, for example, an oxide (e.g., SiO1, Al2O3, etc.), nitride, or oxynitride) may be provided on one of the donor substrate 100 and the or both, prior to the binding process, so that the bonding surface of one of the donor substrate 100 and the receiving substrate 110 or both comprises a surface of the insulating layer 114. The method of Direct molecular bonding may therefore include an oxide-oxide, oxide-silicon or oxide-SiGe bonding process in these embodiments. The insulating layer 114 may include what is often referred to in the art as a "buried oxide layer" or "BOX". The insulating layer 114 may be crystalline or amorphous. The insulating layer 114 may have an average thickness in the bonded structure (which may include the thickness of the two insulating layers 114 if they are deposited on both the donor substrate 100 and the receiving substrate 110 before bonding) included, for example between about 10 nm and about 50 nm, although thinner or thicker insulating layers 114 may be used in embodiments of the present invention. Referring to FIG. 3, after bonding the donor substrate 100 to the recipient substrate 110, the donor substrate 100 may be cleaved along the zone of weakness 112 (FIGS. 1 and 2). The donor substrate 100 may be cleaved or fractured along the zone of weakness 112 by heating it and / or applying a mechanical force thereto. [00501] During the fracturing of the donor substrate 100, as illustrated in FIG. 3, a multi-layer substrate 120 is made, including the receiving substrate 110, which defines a base substrate of the multi-layer substrate 120, the insulating layer 114 which defines a buried oxide layer of the multi-layer substrate 120, the primary semiconductor layer 106 on one side of the buried oxide layer 114, opposite the base substrate 110, and at least a portion of the epitaxial base layer 104 on one side of the primary semiconductor layer 106, opposite the buried oxide layer 114. [0051] The multi-layer substrate 120 is illustrated in FIG. reversed compared to that shown in Figure 4, for further processing. The thickness of the epitaxial base layer 104 of the multi-layer substrate 120 can be selectively controlled by checking the position (depth) of the zone of weakness 112 within the donor substrate 100 (FIG. 1). and / or selectively thinning the portion of the epitaxial base layer 104 of the multi-layer substrate 120, after fracturing the donor substrate 100 along the zone of weakness 112, as previously described with reference to FIG. For example, in some embodiments, the thickness of the epitaxial base layer 104 may be selectively reduced, for example, by at least one of a mechanical polishing operation and a chemical etching operation. after fracturing the donor substrate 100 along the zone of weakness 112. For example, a chemical mechanical planarization (CMP) method may be used to reduce the thickness of the epitaxial base layer 104 a predetermined thickness selected after fracturing of the donor substrate 100 along the zone of weakness 112. This method can also lead to a reduction of the surface roughness of the exposed main surface of the epitaxial base layer 104, and to a thickness more uniform of it, which may also be desirable.
    [0005] With reference to FIG. 5, a first mask layer 122 may be deposited or otherwise provided on the epitaxial basecoat 104 and the primary semiconductor layer 106 within a first region 124A of the multi-substrate. 120. The mask layer 122 may not cover the epitaxial base layer 104 and the primary semiconductor layer 106 within a second region 124B of the multi-layer substrate 120. The first mask layer 122 can be deposited at least substantially continuously on the multi-layer substrate 120, and then covered with patterns to remove the mask layer 122 in the second region 124B of the multi-layer substrate 120, so that the epitaxial basecoat 104 and the primary semiconductor layer 106 is exposed through the first mask layer 122, within the second region 124B of the multi-layer substrate 120.
    [0006] The first mask layer 122 may comprise a single layer of masking material or a plurality of layers of masking material. The composition of the first mask layer 122 may be selected to resist the etching of a chemical reagent used to etch and then remove the mask layer 122 within the second region 124B of the multi-layer substrate 120, as explained below. For example, the first mask layer 122 may comprise an oxide (eg, SiO 2, Al 2 O 3, etc.), a nitride (e.g., Si 3 N 4), or an oxynitride (e.g., silicon oxynitride). ). By way of nonlimiting example, in embodiments where the epitaxial base layer 104 comprises SixGel_x, and the primary semiconductor layer 106, tensile-stressed silicon (sSi), the first mask layer 122 may comprise a multi-layer mask structure, including a first oxide layer (eg, Si09), a nitride layer (eg, Si3N4) on one side of the first oxide layer, opposite the epitaxial base layer 104, and a second oxide layer 12 SiO2) on one side of the nitride layer, opposite the first oxide layer, so that the nitride layer is interposed between the first and the second oxide layers. Referring to Figure After masking the epitaxial base layer 104 and the primary semiconductor layer 106, within the first region 124A of the multi-layer substrate 120, with the first layer of matrix 122 the exposed portion of the epitaxial base layer 104 can be removed from the second region 124B of the multi-layer substrate 120. A driving method can be used to remove the epitaxial base layer 104 from the primary semiconductor layer 106 in the second region 124B. 10056] The etching method employed to remove the epitaxial basecoat 104 from the primary semiconductor layer 106 in the second region 124B may include an acid etching or dry etching method (e.g. reactive ion etching method (RIE)). The etching process may be isotropic or anisotropic. The etchant may be selected to selectively etch the epitaxial basecoat 104 relative to the primary semiconductor layer 106 so that the epitaxial basecoat 104 is preferably removed by the etching method, and the primary semiconductor layer 106 serves as an etch stop layer. In other embodiments, the etching process may stop once the epitaxial basecoat 104 has been removed if no etching reagent is available to selectively remove the epitaxial basecoat 104, without substantially removing the epitaxial basecoat 104. primary semiconductor layer 106. 10057] By way of non-limiting example, in embodiments where the epitaxial base layer 104 comprises Si'Gei .. ', and the primary semiconductor layer 106 of the tensile-stressed silicon (sSI), a dry reactive ion etching (RIE) method can be used to remove the epitaxial basecoat 104. Halogenated component chemistries, including chlorine reactive gases (e.g. C12), fluorine (eg, CF4 or SF6), and / or bromine (eg, HBr) can be used as etching reagents in dry RIE processes. The speed of the RIE driving process can be selectively controlled by adjusting gaseous ratios, pressure, and polarization power in the RIE driver. See, for example, Marcelo SB Castro et al., Selective and Anisotropy Dry Etching of Geoff, Journal of Integrated Circuits and Systems 2013, vol.8, no.2, pp.104-109, which describes these methods of RIE attack, document incorporated here in its entirety by reference. After removal of the epitaxial base layer 104 from the underlying primary semiconductor layer 106, within the second region 124B of the multilayer substrate 120, the mask layer 134 can then be removed therefrom.
    [0007] With reference to FIG. 7, a second mask layer 126 may be deposited or otherwise formed on the exposed primary semiconductor layer 106 within the second region 12413 of the multi-layer substrate 120. It may be that the second mask layer 126 does not cover the epitaxial base layer 104 and the primary semiconductor layer 106, within the first region 124A of the multi-layer substrate 120. The second mask layer 124 may be deposited at the less substantially continuously on the multi-layer substrate 120, and then covered with patterns to remove the mask layer 122 in the first region 124A of the multi-layer substrate 120, so that the epitaxial basecoat 104 and the semi-layer primary conductive layer 106 is exposed through the first mask layer 122 within the first region 124A of the multi-layer substrate 120. The second mask layer 126 may comprise a neck a single masking material or a plurality of layers of masking material. The composition of the second mask layer 126 may be selected to withstand environmental conditions to which it may be exposed during a subsequent atomic diffusion process on the epitaxial basecoat 104 and the primary semiconductor layer 106 at the same time. interior of the first region 124A of the multi-layer substrate 120, as described below with reference to Figures 8A-8C. For example, the second mask layer 126 may comprise an oxide (eg, SiO 2, AlO 3, etc.), a nitride (e.g., Si 3 N 4), or an oxynitride (e.g., silicon oxynitride). ). By way of non-limiting example, in embodiments where the epitaxial base layer 104 comprises SixGel. ', And the primary semiconductor layer 106, tensile-stressed silicon (sSi), the second mask layer 126 may include a multi-layer mask structure including an oxide layer (eg, Si09), and a nitride layer (e.g., Si3N4) on one side of the oxide layer, opposite of the epitaxial base layer 104. After masking the primary semiconductor layer 106, within the second region 124B of the multi-layer substrate 120, with the second mask layer 126, a method of condensation (often referred to as a "thermal mixing" process) or other type of process may be used to diffuse elements of the epitaxial base layer 104 within the first region 124A into the primary semiconductor layer underlying 106, so as to reduce selectively the tensile stress, and / or increasing the compressive stress, in the primary semiconductor layer 106, within the first region 124A, relative to the stress level of the primary semiconductor layer 106, at within the second region 1248 of the multi-layer substrate 120. The presence of the second mask layer 126 and the absence of the epitaxial base layer 104 in the second region 124B can prevent the diffusion of elements in the primary semiconductor layer 106, within the second region 124B, so that the stress in the primary semiconductor layer 106 is retained during the condensation process performed on the first region 124A of the multi-layer substrate 120. In In other words, the condensation process can only be performed on the first region 124A of the multi-layer substrate 120, and not on the second region 124B thereof. This condensation process is described below with reference to Figures 8A-8C. Figure 8A is an enlarged view of a portion of the multi-layer substrate 120, shown in Figure 6, within the first region 124A. The condensation process may involve subjecting the multilayered substrate 120, with the primary semiconductor layer 106, masked within the second region 124B thereof, to an oxidation process in a furnace at high temperatures (eg, between about 900 ° C and about 1150 ° C) in an oxidizing atmosphere (eg, dry 02). With reference to FIG. 8B, the oxidation process may lead to the formation of an oxide layer 136 on the surface of the multi-layer substrate 120, and may result in the diffusion of elements of the epitaxial base layer 104 in the primary semiconductor layer 106, within the first region 124A of the multi-layer substrate 120. Over time, the boundary or interface between the epitaxial base layer 104 and the primary semiconductor layer 106 can become indiscreet, since the elements of the epitaxial base layer 104 are incorporated in the growing oxide layer 136 and / or diffuse and are incorporated in the underlying semiconductor layer 106. [0063] In embodiments wherein the primary semiconductor layer 106 comprises tensile-stressed silicon (sSi), and the Si'Ger 'epitaxial base layer 104, the oxide layer 136 may comprise silicon dioxide (SiO 2), and the germanium of the base layer The SiGei.sup. + pit, 104 can diffuse into the constrained silicon (sSi) of the primary semiconductor layer 106, which transforms the sSi 106 constrained semiconductor layer into a SiyGei_y constrained primary semiconductor layer 106. The oxide layer 136 may form on the surface of the epitaxial base layer 104 and grow in thickness in the multi-layer substrate 120, through the dissolving epitaxial base layer 104, and in the primary semiconductor layer 106. When the thickness of the oxide layer 136 increases during the germanium condensation process, the thickness of the primary semiconductor layer 106 decreases, and the germanium concentration in the primary semiconductor layer 106 increases until the obtaining a primary semiconductor layer 106, having a desired concentration of germanium, in the primary semi-conductor layer of the SiyGei_y 106 constraint, as illustrated in Figure 8C. The diffusion of the germanium in the primary semiconductor layer 106 can cause a decrease in the tensile stress within the layer and lead to the occurrence of a compressive stress therein. After the condensation process, the primary semiconductor layer 106, inside the first region 124A, can be in a tensile stress state, lower than a tensile stress in the primary semiconductor layer 106, within the second region 124B, the primary semiconductor layer 106, within the first region 124A, may be, at least, in a substantially relaxed state, free from tensile or compressive stress or the primary semiconductor layer 106, within the first region 124A, may be in a state of compressive stress. The oxide layer 136 may optionally be removed from the primary semiconductor layer 106 within the first region I 24A of the multi-layer substrate 120 after completion of the condensation process. The oxide layer 136 may be removed by an acid etching or dry process. The condensation process may result in a decrease in the thickness of the primary semiconductor layer 106 within the first region 124A of the multilayer substrate 120 as can be seen by comparing FIGS. 8A and 8C. . In some embodiments, after performing the method of condensing and removing the oxide layer 136, an additional semiconductor material may be selectively grown by epitaxial growth on the primary semiconductor layer 106, within the first region 124A of the multi-layer substrate 120, without epitaxial growth of an additional semiconductor material on the primary semiconductor layer 106, within the second region 124B of the multi-layer substrate 120. The semi-conducting material Additional conductor may have the same composition and state of stress as the underlying semiconductor material of the primary semiconductor layer 106, within the first region 124A of the multi-layer substrate 120. Selective epitaxial growth additional semiconductor material may be used to thicken the primary semiconductor layer 106, within the premature semiconductor layer region 124A of the multi-layer substrate 120, so that a thickness of the primary semiconductor layer 106, within the first region 124A, is at least substantially equal to a thickness of the primary semiconductor layer 106, within the second region 124B, which has not been subjected to the condensation process. The condensation process can lead to improved mobility of the holes, inside the primary semiconductor layer 106, in the first region 124A of the multi-layer substrate 120, which may be desirable to form transistors PMOS, such as planar technology FET transistors or finned FET transistors having transistor channel structures including regions of the primary semiconductor layer 106, within the first region 124A of the multi-layer substrate 120 The primary semiconductor layer 106, within the second region 124B of the multi-layer substrate 120, can remain in a state of tensile stress which may be desirable to form NMOS transistors, such as FET transistors. planar technology or finned FET transistors having transistor channel structures including regions of the primary semiconductor layer 106, within the second region 124B of the multi-layer substrate 120.
    [0008] Referring to Figure 9, after providing multi-layer substrate 120, the latter may be etched to define finned structures 132 each of which may comprise a portion of the primary semiconductor layer 106. Each of the finned structures 132 It can be sized and configured for use in a finned FET. The etching method can be performed, for example, by depositing a layer layer over a multilayered substrate 120, forming patterns on the mask layer. include openings at locations where it is desirable to etch into and through the epitaxial base layer 104 and the primary semiconductor layer 106, and then etch the primary semiconductor layer 106 through the mask layer motifs. Other methods known in the art can be used to form such finned structures 132, such as spacer-defined double masking (SDDP) methods, also known in the art as transfer methods. picture on side wall. The etching process may comprise an acid etching method or a dry etching method (e.g., reactive ion etching (RIE) method). The etching process may include an anisotropic etching process to provide fin structures 132 having generally vertical sidewalls. The etch reagent may be selected to selectively etch the epitaxial basecoat 104 and the primary semiconductor layer 106, relative to the underlying BOX layer 114, so that the BOX layer 114 can serve as the stop attack. By way of nonlimiting example, in embodiments where the primary semiconductor layer 106 comprises tensile-stressed silicon (sSi), inside the second region 124B, and SiyGel_y constrained in compression within the first region 124A, a dry reactive ion etching (RIE) method may be employed employing halogenated component based chemistries, including chlorine reactive gases (e.g. eg, C12), fluorine (eg, CF 4 or SFs), and / or bromine (eg, FIBr) as the driving reagents. The finned structures 132 may include a first plurality of fins 32A intended to be fins of P-type finned FET transistors, and a second plurality of fins 132B intended to be fins of finned FET transistors. each of the first plurality of fins 132A may comprise a portion of the primary semiconductor layer 106, within the first region 124A of the multi-layer substrate 120 and each of the second plurality of fins 132B may comprise a portion of the primary semiconductor layer 106 within the second region 124B of the multi-layer substrate 120. As a result, the first plurality of fin structures 132A may be in a different constrained state by relative to the second plurality of fin structures 132B. In particular, the second plurality of fin structures 132B. may be in a state of tensile stress, and the first plurality of winged structures I 32A in a state of reduced tensile stress (relative to the second plurality of winged structures 132B), in a relaxed state at least substantially free of stress in tension or compression or in a state of compressive stress. In some embodiments, the fin structures 132 may have one or more dimensions (eg, length, width or height) below a critical dimension at which the material of the finned structures 132 will relax. either spontaneously or during further processing at elevated temperatures. In some embodiments, finned structures 132 may be formed to achieve an average blade width 1 (see FIG. 10) of about 30 nm or less, about 20 minutes or less, or about 15 nm or less. In the methods described above, the epitaxial base layer 104 may be used as a base layer on which the primary semiconductor layer 106 is initially formed by epitaxial growth, so that the primary semiconductor layer 106 is in a constrained state, as described with reference to Figure 1, and can be used later to modify a stress state of a portion of the primary semiconductor layer 106, in the condensation process, as described with reference to Figures 8A-8C. As described above, the first plurality of fin structures I32A, and the second plurality of fin structures 132B can be formed together in a common masking and etching method, as described with reference to FIG. 9. The resulting structure formed by the methods described herein includes a first plurality of fin structures 132A and a second plurality of fin structures 132B disposed on the buried oxide layer 114 in a common plane on one side thereof. 1, opposite the base substrate 110. Each of the first plurality of fin structures 132A includes a primary semiconductor layer 106 including two or more elements (eg, silicon and germanium). Each of the second plurality of fin structures 132B comprises a non-condensed primary semiconductor layer 106. In addition, the fin structures 132 of the second plurality of fin structures 132B exhibit a crystallographic stress differing from a crystallographic stress of the fin structures 132 of the first plurality of finned structures 132A. For example, the fin structures 132 of the second plurality of fin structures 132B may be in a tensile stress state, and the fin structures 132 of the first plurality of fin structures 132A may be in a state of reduced tensile stress, a relaxed stress state (no stress) or a compressive stress state. After forming the first plurality of fin structures 132A and the second plurality of fin structures 132B, as described above, a first plurality of PMOS finned FET transistors may be formed, including the first plurality of structures. 132A finned fins and a second plurality of NMOS finned FET transistors may be formed, including the second plurality of finned structures 132B. FIG. 10 illustrates a simplified, non-limiting example of one embodiment of a finned FET configuration that can be fabricated using the first plurality of IA fin structures 32A and / or the second plurality of IET structures. fins 132B, in accordance with the embodiments of the present invention. It will be appreciated that many different configurations of finned FETs are known in the art, and may be employed in accordance with the embodiments of the invention, and the finned FET structure shown in Fig. 10 is disclosed merely as an example of these fin FET structures. As shown in FIG. 10, a fin FET 140 comprises a source region 142, a drain region 144, and a channel extending between the source region 142 and the drain region 144. The channel is defined by and comprises a fin 132, such as either a first fin structure 132A or a second fin structure 132B. In some embodiments, the source region 142 and the drain region 144 may include or be defined by longitudinal end portions of a fin structure 132. A conductive gate 146 extends contiguously over at least a portion of the fin structure 132 between the source region 142 and the drain region 144. The gate 146 may be separated from the fin structure 132 by a dielectric material 148. The gate 146 may include a multilayer structure and conductive layers and / or semiconductors. A low resistance layer including a metal, a metal compound or both, such as conductive silicide, may be deposited on the source region 142 and / or the drain region 144 to form electrical contacts therein.
    [0009] Advantageously, the tensile stress in the channel can increase the performance of NMOS finned FET transistors and reduce the threshold voltage, while a reduced tensile stress (eg, less tensile stress, not stress in tension or compression or compressive stress) in the channel, can increase the performance of PMOS finned FET transistors, and reduce the threshold voltage. For some functions, constrained devices are advantageous because of the need for high performance; for others, the performance is not as important, but a threshold voltage is advantageous. With the embodiments of the present invention, the manufacturer can selectively incorporate different voltage / stress levels in the crystal lattices of different fin FETs in the same device into a common fin FET plane. Although the above methods and structures are described in connection with finned FET structures, it will be appreciated that additional embodiments of the invention may include forming conventional FET structures other than FET structures to fins, and a plurality of conventional P type FET CMOS transistors may be fabricated by means of the primary semiconductor layer 106, within the first region 124A of the mufti-layer substrate 120, and a plurality of FET CMOS transistors conventional N-type can be made by means of the primary semiconductor layer 106, within the second region 124B of the multi-layer substrate 120. Non-limiting examples of additional embodiments of the invention are shown below. Embodiment 1: A method of manufacturing a semiconductor structure comprising: providing a multi-layer substrate, including: a base substrate, an oxide layer buried on a surface of the base substrate , a primary semiconductor layer constrained on one side of the buried oxide layer, opposite the base substrate, and an epitaxial base layer on one side of the strained semiconductor layer, as opposed to the buried oxide layer; diffusing elements of the epitaxial base layer in the constrained primary semiconductor layer, within a first region of the multi-layer substrate, without diffusion of elements of the epitaxial base layer in the semiconductor layer constrained primary within a second region of the multi-layer substrate, and enriching a concentration of diffused elements in the primary semiconductor layer, within the first region, so that a state constrained in the primary semiconductor layer, within the first region, differs from a constrained state in the primary semiconductor layer, within the second region; and forming a first plurality of transistor channel structures, each comprising a portion of the primary semiconductor layer, within the first region of the multi-layer substrate, and a second plurality of channel structures transistor, each comprising a portion of the primary semiconductor layer, within the second region of the multi-layer substrate. Embodiment 2: The method of Embodiment 1, further comprising selecting the constrained semiconductor layer to include constrained silicon. Embodiment 3: The method of Embodiment 2, further comprising selecting the constrained semiconductor layer to include tensile stressed silicon. Embodiment 4: The method of any one of embodiments 1 to 3, further comprising selecting the epitaxial base layer to comprise SixGel, wherein x is between about 0, 1 and 0.99, and wherein the diffusion of elements of the epitaxial base layer into the constrained primary semiconductor layer comprises the diffusion of germanium into the strained primary semiconductor layer, within the first region of the multi-layer substrate. Embodiment 5: The method of any one of Embodiments 1 to 4, wherein forming a first plurality of transistor channel structures and forming the second plurality of channel-channel structures. transistor, comprises etching through the primary semiconductor layer and defining finned structures, each of which comprises a portion of the primary semiconductor layer, each of the fin structures being sized and configured to be used in a finned FET. Embodiment 6: The method of any one of embodiments I to 5, wherein the provision of the multi-layer substrate comprises: the epitaxial growth of the semiconductor layer constrained on the epitaxial base layer, on a donor substrate, to form a donor structure; implanting ions into the donor structure and forming a zone of weakness within the donor structure; bonding the donor structure to a recipient substrate comprising the base substrate; and cleaving the donor structure along the area of weakness to transfer the strained semiconductor layer and the epitaxial base layer onto the base substrate.
    [0010] Embodiment 7: The method of Embodiment 6, wherein bonding the donor structure to the recipient substrate comprises providing an oxide layer to one or both of the donor structure and the substrate. recipient, and the binding of the donor structure to the recipient substrate by means of a direct binding method. Embodiment 8: The method of Embodiment 6 or 7 further comprising providing the zone of weakness within a substantially homogeneous region of the donor substrate comprising the epitaxial basecoat. Embodiment 9: The method of any one of Embodiments 1 to 8, wherein the diffusion of elements of the epitaxial base layer into the strained primary semiconductor layer, within the first multi-layer substrate region, comprises stress relaxation in the primary semiconductor layer, within the first region of the multi-layer substrate.
    [0011] Embodiment 10: The method of any one of embodiments 1 to 9, wherein the diffusion of elements of the epitaxial base layer in the stressed primary semiconductor layer, within the first region of the substrate. multi-layer comprises the introduction of a compressive stress in the primary semiconductor layer, 0 within the first region of the multi-layer substrate. Embodiment 11: The method of any one of embodiments 1 to 10, wherein the diffusion of elements of the epitaxial base layer in the constrained primary semiconductor layer, within the first region. multi-layer substrate comprises increasing the mobility of the holes in the primary semiconductor layer within the first region. Embodiment 12: The method of any one of embodiments 1 to 11, wherein the diffusion of elements of the epitaxial base layer into the constrained primary semiconductor layer, within the first region. multi-layer substrate comprises performing a condensation process on the primary semiconductor layer within the first region of the multi-layer substrate. Embodiment 13: Process of Embodiment 12, wherein the realization of a condensation process on the primary semiconductor layer, within the first region of the multi-layer substrate, comprises the oxidizing a portion of the primary semiconductor layer within the first region of the multi-layer substrate. Embodiment 14: The method of any of Embodiments I to 13, further comprising forming a plurality of P-type FET transistors, comprising the first plurality of channel structures. transistor, and forming a plurality of N-type FET transistors, comprising the second plurality of transistor channel structures. Embodiment 15: A method of manufacturing a semiconductor structure 30 comprising: providing a multi-layer substrate, including: a base substrate, an oxide layer buried on a surface of the substrate; base, a primary semiconductor layer 23 constrained to one side of the buried oxide layer, opposite the base substrate, and an epitaxial base layer on one side of the strained semiconductor layer, to the opposite of the buried oxide layer; masking a first region of the multi-layer substrate with a first masking layer, and removing a portion of the epitaxial base layer from a second region of the multi-layer substrate; removing the first masking layer from the first region of the multi-layer substrate, and masking the second region of the multi-layer substrate with a second mask layer; diffusing elements of the epitaxial base layer in the strained primary semiconductor layer, within the first region of the multilayer substrate, and changing a state of stress of the primary semiconductor layer, to the interior of the first region of the multi-layer substrate, without diffusion of elements in the constrained primary semiconductor layer, within the second region of the multi-layer substrate; and forming a first plurality of transistor channel structures, each comprising a portion of the primary semiconductor layer, within the first region of the multilayer substrate, and a second plurality of channel channel structures. transistor, each comprising a portion of the primary semiconductor layer, within the second region of the multilayer substrate. Embodiment 16: The method of Embodiment 15, further comprising selecting the constrained semiconductor layer to include tensile-stressed silicon. Embodiment 17: The method of Embodiment 15 or 16, further comprising selecting the epitaxial basecoat to comprise at least substantially relaxed SixGel-x, wherein x is between about 0.01. and about 0.99, and, wherein the diffusion of elements of the epitaxial base layer in the strained primary semiconductor layer, within the first region of the mufti-layer substrate, comprises the diffusion of germanium into the constrained primary semiconductor layer, within the first region of the multi-layer substrate. Embodiment 18: The method of any one of Embodiments 15 to 17, further comprising forming a plurality of P-type FET transistors, comprising the first plurality of transistor channel structures. , and forming a plurality of N-type FET transistors, including the second plurality of transistor channel structures. Embodiment 19: A semiconductor structure including a multilayer substrate, comprising: a base substrate, an oxide layer buried on a surface of the base substrate, and a primary semiconductor layer on one side of the substrate; buried oxide layer, opposite to the base substrate, a portion of the primary semiconductor layer, within a first region of the multi-layer substrate comprising SiyGel_y, wherein y is between 0.20 and about 0.99, a portion of the primary semiconductor layer, within a second region of the multi-layer substrate, comprising strained Si in tension; wherein the portion of the primary semiconductor layer within the first region of the multilayer substrate has a crystallographic stress differing from a crystallographic stress of the portion of the primary semiconductor layer, within the second region of the multilayer substrate. [00101] Embodiment 20: Semiconductor structure of Embodiment 19, further comprising a first plurality of P-type FET transistors each comprising a portion of the primary semiconductor layer, within the first region of the multi-layer substrate, and a second plurality of N-type FET transistors, each comprising a portion of the primary semiconductor layer within the second region of the multi-layer substrate. The examples of embodiments of the invention described above do not limit the scope of the invention, since they constitute only simple examples of embodiments of the invention which is defined by the scope of the appended claims and their legal equivalents. All equivalent embodiments are intended to be included within the scope of the present invention. Of course, various modifications of the invention, in addition to those indicated and described herein, such as other useful combinations of elements presented, will be apparent to those skilled in the art. In other words, one or more features of an exemplary embodiment described herein may or may be combined with one or more features of another exemplary disclosed embodiment. here, to provide additional embodiments of the invention. These modifications and embodiments are also intended to be included in the scope of the appended claims. 25
    权利要求:
    Claims (3)
    [0001]
    REVENDICATIONS1. A method of manufacturing a semiconductor structure, comprising: providing a multi-layer substrate, including: a base substrate, an oxide layer buried on a surface of the base substrate, a primary semiconductor layer stress on one side of the buried to buried oxide layer, opposite the base substrate, and an epitaxial base layer on one side of the stressed semiconductor layer, opposite the buried oxide layer ; diffusing the epitaxial base layer in the constrained primary semiconductor layer within a first region of the multi-layer substrate without diffusing elements of the epitaxial base layer into the semiconductor layer constrained primary within a second region of the multi-layer substrate, and enriching a concentration of diffused elements in the primary semiconductor layer within the first region, so that a state of stress in the primary semiconductor layer, within the first region, differs from a state of stress in the primary semiconductor layer, within the second region; and forming a first plurality of transistor channel structures, each comprising a portion of the primary semiconductor layer, within the first region of the multi-layer substrate, and a second plurality of channel-channel structures. transistor, each comprising a portion of the primary semiconductor layer within the second region of the multi-layer substrate.
    [0002]
    The method of claim 1, further comprising selecting the constrained semiconductor layer to include constrained silicon. 30
    [0003]
    The method of claim 2, further comprising selecting the constrained semiconductor layer to include tensile stressed silicon. The method of claim 2, further comprising selecting the epitaxial basecoat to comprise SixGei_x, wherein x is from about 0.01 to about 0.99, and wherein the diffusion of the epitaxial base layer in the constrained primary semiconductor layer, comprises the diffusion of germanium in the strained primary semiconductor layer, within the first region of the multi-layer substrate. The method of claim 1, wherein forming a first plurality of transistor channel structures and forming the second plurality of transistor channel structures comprises driving through the primary semiconductor layer and defining finned structures, each including a portion of the primary semiconductor layer, each of the finned structures being sized and configured for use in a finned FET. The method of claim 1, wherein providing the multi-layered substrate comprises: epitaxially growing the semiconductor layer constrained on the epitaxial base layer on a donor substrate to form a donor structure; implanting ions into the donor structure and forming a zone of weakness within the donor structure; bonding the donor structure to a recipient substrate comprising the base substrate; and cleaving the donor structure along the zone of weakness to transfer the stressed semiconductor layer and the epitaxial base layer onto the base substrate 7. The method of claim 6, wherein bonding the donor structure to the substrate substrate base includes providing an oxide layer on one or both of the donor structure and the receiving substrate; and binding the donor structure to the recipient substrate by a direct binding method. The method of claim 6, further comprising disposing the zone of weakness within a substantially homogeneous region of the donor substrate comprising the epitaxial basecoat. The method of claim 1 wherein the diffusion of elements of the epitaxial base layer into the strained primary semiconductor layer within the first region of the multi-layer substrate comprises stress relaxation in the primary semiconductor layer, within the first region of the multi-layer substrate. 10. The method of claim 1, wherein the diffusion of elements of the epitaxial base layer in the strained primary semiconductor layer, within the first region of the multilayer substrate, comprises the introduction of a compressive stress in the primary semiconductor layer, within the first region of the multi-layer substrate. 11. The method of claim 1, wherein the diffusion of elements of the epitaxial base layer in the strained primary semiconductor layer, within the first region of the multi-layer substrate, comprises increasing the the mobility of the holes in the primary semiconductor layer, within the first region. The method of claim 1, wherein the diffusion of elements of the epitaxial base layer in the strained primary semiconductor layer, within the first region of the multi-layer substrate, comprises carrying out a condensation process on the primary semiconductor layer, within the first region of the multi-layer substrate. The method of claim 12, wherein performing a condensation process on the primary semiconductor layer, within the first region of the multi-layer substrate, comprises oxidizing a portion of the primary semiconductor layer, within the first region of the mei-layer substrate. The method of claim 1, further comprising forming a plurality of P-type FET transistors, comprising the first plurality of transistor channel structures, and forming a plurality of N-type FET transistors, comprising the second plurality of transistor channel structures. A method of manufacturing a semiconductor structure, comprising: providing a multi-layer substrate, including: a base substrate, an oxide layer buried on a surface of the base substrate, a semi-layer primary conductive strand on one side of the buried oxide layer, opposite the base substrate, and an epitaxial base layer on one side of the strained semiconductor layer, opposite the buried oxide; masking a first region of the multi-layer substrate by a first mask layer, and removing a portion of the epitaxial base layer from a second region of the multi-layer substrate. removing the first mask layer from the first region of the multi-layer substrate, and masking the second region of the multi-layer substrate by a second mask layer. The diffusion of elements of the epitaxial base layer in the strained primary semiconductor layer inside the first region of the multi-layer substrate, and the modification of a state of stress of the semiconductor layer primary, within the first region of the multi-layer substrate, without diffusion of elements in the constrained primary semiconductor layer, within the second region of the multilayer substrate; and forming a first plurality of transistor channel structures, each comprising a portion of the primary semiconductor layer, within the first region of the multi-layer substrate, and a second plurality of channel-channel structures. transistor, each comprising a portion of the primary semiconductor layer within the second region of the multi-layer substrate. The method of claim 15, further comprising selecting the constrained semiconductor layer to include tensile stressed silicon. The method of claim 16, further comprising selecting the epitaxial basecoat to comprise at least substantially relaxed SixGei, x, wherein x is from about 0.01 to about 0.99, and , wherein the diffusion of elements of the epitaxial base layer in the stressed primary semiconductor layer, within the first region of the multi-layer substrate, comprises the diffusion of germanium in the stressed primary semiconductor layer, inside the first region of the multi-layer substrate. The method of claim 17, further comprising forming a plurality of P-type FET transistors, comprising the first plurality of transistor channel structures, and forming a plurality of N-type FET transistors, comprising the second plurality of transistor channel structures. A semiconductor structure including a multi-layer substrate, comprising: a base substrate, an oxide layer buried on a surface of the base substrate, and a primary semiconductor layer on one side of the oxide layer buried, opposite the base substrate, a portion of the primary semiconductor layer, within a first region of the multi-layer substrate comprising SiyGel_y, wherein y is between about 0.20 and about 0.99, a portion of the primary semiconductor layer, within a second region of the multi-layer substrate having strained Si in tension; wherein, the portion of the primary semiconductor layer, within the first region of the multi-layer substrate, has a crystallographic stress differing from a crystallographic stress of the portion of the primary semiconductor layer, at least one interior of the second region of the multi-layer substrate. A semiconductor structure according to claim 19, further comprising a first plurality of P-type FET transistors each comprising a portion of the primary semiconductor layer, within the first region of the multi-layer substrate, and a second plurality of N-type FET transistors, each comprising a portion of the primary semiconductor layer within the second region of the multi-layer substrate. 31
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    申请号 | 申请日 | 专利标题
    US14/489,817|US9219150B1|2014-09-18|2014-09-18|Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures|
    US14489817|2014-09-18|
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